(1) Field of the Invention
The present invention generally relates to fabrication of semiconductor devices. More specifically, the present invention relates to fabrication of integrated circuits that utilize prefabricated transistor layers.
(2) Description of Related Art
Modern integrated circuits are generally made up of a silicon substrate containing millions of active and passive devices including transistors, capacitors, resistors, etc. Until recently, the semiconductor industry's focus was on reducing the two dimensions, (X-Y) in a Cartesian system of coordinates, of the transistors to reduce the size of the integrated circuit. However, as integration in two dimension has become more and more difficult due to limitations of lithography tools, the exploitation of the third dimension (Z dimension in a Cartesian system of coordinates) has become increasingly attractive.
FIG. 1 illustrates a conventional integrated circuit 100 that includes a substrate 102 (typically made of silicon) onto which a very large number of active devices (transistors 104) are fabricated. Transistors 104 are intercoupled therebetween and to other devices, therefore forming various circuits, by way of an interconnect system that includes metal lines (106). The metal lines may further be connected to other circuits. The various circuits formed are further coupled, by well-known techniques, to bond pads 108 of the integrated circuit. Transistors 104 are therefore located on a single layer of silicon at the bottom of the integrated circuit. When the dimension of the gates of transistors 104 goes some way beyond 193 nanometers, which is the shortest wave length of the light used in the present day photolithography process, integration of transistors becomes problematic as lithography tools that are utilized in the process of fabrication of these transistors reach the limit of their performance. One solution to increasing integration without further having to minimize transistors' gates dimensions and thus without resorting to new lithography tools, is to build up further layers of transistors in a third dimension (Z dimension) as illustrated in FIG. 2.
FIG. 2 illustrates an integrated circuit that includes a first silicon substrate (base substrate 202) onto which are built a first layer (film) 205 of active devices 204. A second layer (film) 206 of active devices 208 may be envisioned as being further built in the Z dimension (vertically in the Figure). Interconnect lines 207 intercouple the active devices 208 of second layer 206 to the active devices 204 of first layer 205. The second layer 206 of active devices 208 may be coupled to the outside world via bond pads 210.
In the image area (imaging) attempts have been made to integrate transistors in the third dimension. For example, some digital cameras use chips that have at the bottom thereof (at the base silicon substrate) transistors for logical operations and on top of those transistors are built image sensors. For example, image sensor arrays may be built in the third dimension and used as light sensors. However, these transistors do not have good conducting properties, and therefore their performance is weak. These second-layer transistors are not made of a single-crystal silicon but are made of a polycrystalline silicon or amorphous silicon. The problem in providing a second layer of active devices (transistors) made of a single silicon crystal is that the fabrication of the second level of transistors requires processing steps that are performed at temperatures that are well beyond the temperature that the interconnect system may withstand. For example, at 400.degree. or 450.degree. Celsius, the metal lines begin to melt. It is desirable to provide an integrated circuit that utilizes at least two layers of transistors that offer competitive performance at lower costs. It is desirable to provide an integrated circuit with a second level of transistors in the Z dimension made of a single crystal silicon.